Blanking circuit for a plural cathode display tube



July so, 1968 D. M. BARTON 3,395,268

BLANKING CIRCUIT FOR A PLURAL CATHODE DISPLAY TUBE Filed June 10, 1966 Wo I 2 3 4 5 s 1 a 9 24 26 0 W HGI Et EVEN 2W OORI 20R3 I I 32 TOADDITIONAL 4 CR5 I I S' I'ISITISIII' T g& K GATING TRANSISTORS 60R? I I8 0R 9 I I FIGS 50 I I 3 5 1 9 I INVENTOR DAVID M. BARTON United StatesPatent 3,395,268 BLANKING CIRCUIT FOR A PLURAL CATHODE DISPLAY TUBEDavid M. Barton, Bridgeton, Mo., assignor to Monsanto Company, St.Louis, Mo., a corporation of Delaware Filed June 10, 1965, Ser. No.462,894 1 Claim. (Cl. 23592) ABSTRACT OF THE DISCLOSURE A transistorizedcircuit for connection between a counter and a numerical display tube toprevent the initiation of the display tube by the signals on the counteroutput leads while the counter is accumulating input actuation. Aseparate driving transistor for each indication on the display tube isenergized only by the coincidence of unique conditioning signal and acommon driving signal. The conditioning signals are applied to the basesrespectively of the transistors. The driving signal is applied through aseparate gating transistor to the emitters of a plurality oftransistors. The driving and conditioning signals combine to select theparticular transistor to be energized but a blanking pulse applied tothe gating transistor prevents all transistors from being energized.

This invention relates to an electronic blanking circuit for blanking anilluminated read-out display during selected intervals.

The invention pertains to a circuit configuration for blanking orturning off a read-out device for a digital counter, such as a BurroughsNixie numeric display tube. Such a tube is customarily operated from acounter by means of a coded arrangement of wires selectively conditionedin response to the state of the counter. The cathodes of the Nixie tubemay be driven by individual transistors, each having its collectorconnected to the related cathode of the Nixie tube, its base connectedto one of the coded wires from the counter and its emitter connected toanother of the coded wires from the counter, the coding scheme requiringan input on the base and emitter to .make the selected transistorconduct.

In digital measuring applications having display tube read-outs, e.g.,digital voltmeter with read-out, a blur appears on the read-out tubebetween readings because an internal counter which is accumulating toform the answer is connected via a decoder circuit directly to theread-out device. The blur on the read-out device is annoying to theuser. One scheme in the prior art for eliminating blur is to employ astorage means within the digital voltmeter. The storage means remembersthe previous reading and stores it during the counting interval. At theend of the counting interval and on command of a given signal, thecounter output is read by the storage means. Since the read-out displaytube receives its information from the storage means and not from thecounter, no blur occurs. Memories such as this are fairly expensive andthus there is an obstacle to their use in inexpensive measurementapplications.

In accordance with the present invention, a simple, inexpensiveelectronic circuit is provided for connection between the display tubeand the counter and decoder circuits for blanking the display tubesduring the counting interval. Blanking transistors are inserted inseries with the drive lines leading to the emitters of the drivingtransistors. By applying a blanking signal to the base of the seriesconnected blanking transistors, the driving current to the emitters ofthe driving transistors can be blocked and the display tube will remaindark. It has been demonstrated that in an instrument in which thecounting interval is short, there is little or no annoyance to the humaneye if the read-out is simply blanked during this interval.

It is therefore an object of the present invention to provide a new andimproved circuit for blanking a display tube during selected intervals.

A further object of the present invention is to provide a new, improvedand inexpensive circuit for blanking a read-out tube during selectedintervals.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

In the drawings:

FIGURE 1 is a schematic diagram of a preferred embodiment of theinvention;

FIGURE 2 is a partially schematic and partially block diagram of anembodiment of the invention used in conjunction with a particularcounter and decoding circuit;

FIGURE 3 is a series of time-waveforms helpful in explaining theoperation of FIGURE 2.

Referring to FIGURE 1, there is shown a read-out display tube 24 whichmay be a Burroughs Nixie tube, having an anode 26 connected to a voltagesource V, and cathodes 28. Each cathode 28 corresponds to a particularcharacter of the tube which is displayed when the corresponding cathodeis energized. The display tube 24 is shown open ended to indicate thatthe tube may include additional cathodes not shown. Driving transistors20 and 22 conduct current to the cathodes 28 of the display tube 24,thus illuminating the corresponding characters. Terminals 10 and 12 areconnected to bases 40 and 46 of transistors 22 and 20, respectively.Collectors 42 and 48 of the driving transistors are connected to thecathodes 28 of the display tube, and emitters 38 and 44 are connected toa driving line 36 which supplies driving voltage to the drivingtransistors. A gating or blanking transistor 18, having an emitter 30,base 32 and collector 34 is connected via collector 34 to the emitterdrive line 36. It should be noted that emitter drive line 36 may beconnected to the emitters of additional driving transistors not shown.Emitter 30 of transistor 18 is connected to a terminal 14 and base 32 isconnected via a current limiting resistor 28 to the blanking inputterminal 16. Blanking input terminal 16 may also be connected toadditional blanking or gating transistors, not shown in FIGURE 1. Thenumber of driving transistors used and the number of blankingtransistors necessary for a given number of driving transistors may varyand is dependent upon the particular coding scheme used in the displaycircuitry.

Transistor 18 is a blanking transistor which acts when turned off toblank all of the characters of the display tube which are driven by thedriving transistors and which have their emitters connected to thecollector of the blanking transistor. .When terminal 16 is several voltspositive, transistor 18 is in the on condition and control of thedriving transistors is determined by the conditioning signals applied totheir bases and emitters, respectively. For example, assuming transistor18 is on, driving transistor 20 is controlled by the conditioningsignals applied to terminals 12 and 14. A conditioning signal atterminal 12 is a slightly positive signal and a conditioning signal atterminal 14 is a grounded or slightly negative signal. With conditioningsignals applied in coincidence at terminals 12 and 14, and assumingtransistor 18 is on, driving transistor 20 will turn on thus causing a.display character associated with driving transistor 20 to beilluminated. If a conditioning signal is present on only one of theinput terminals, transistor 20 will not turn on and thus its associatedcharacter will not be illuminated.

In the illustration shown in FIGURE 1, if tube 24 is a Nixie tube havingten cathodes, corresponding to the decimal character through 9, thepresence of a conditioning signal at terminal 12 and a conditioningsignal at terminal 14 will turn on driving transistor 20 and the Nixietube will indicate a 0 reading. The presence of a conditioning signal atterminal and a conditioning signal at terminal 14 will turn on drivingtransistor 22 resulting in the display of decimal character 1". Theremainder of the driving transistors are not shown but it should beapparent that they would operate in the same manner as drivingtransistors and 22 The input signals to the bases of the drivingtransistors may be the output leads from a decoding circuit whichprovides only one output at a time to any of the base terminals 10, 12,etc., in order to prevent conduction of more than one driving transistorat any one time. The decoding circuit may be connected to the output ofan electronic counter which is used, for example, in a digitalvoltmeter. The particular decoding circuit and/or counter form no partof the present invention which consists of a novel blanking circuit thatmay be used with various types of counters and decoding schemes.

If the circuit is used with an electronic counter and decoding circuitas explained above, during the accumulation or counting period of thecounter, the reading of the Nixie tube will be changing in accordancewith the variation of the counditioning signals applied to baseterminals of the driving transistors by the decoding circuit. The lattersituation creates a visual blur on the Nixie read-out tube which isannoying to the user. In order to eliminate the blur it becomesnecessary to prevent the read-out tube from responding to the decoderoutput during the accumulation or counting period. This may be done inthe present invention by applying a blanking pulse to terminal 16. Theblanking pulse which in the embodiment shown is a grounded or slightlynegative signal turns off blanking transistor 18 which in turnelectrically disconnects terminal .14 from the emitter drive line 36.All of the driving transistors are thus prevented from receiving aconditioning signal appearing at terminal 14 and thus remain in theirnon-conducting condition. When the counting period is over, the blankingsignal is removed allowing the driving transistors to respond to theparticular count of the counter and allowing the Nixie display tube todisplay the new count.

In FIGURE 2 there is shown a specific arrangement of the blankingcircuit for use with a particular coding arrangement. Terminal 84 may bethe output connection of any measuring circuit, e.g., the output of ananalog-totime voltage converter. Input terminal 84 is connected as oneinput to AND gate 82, the other input being supplied a with pulses froma pulse source 88. Terminal 84 is also connected to the blanking circuit50 via lead 86 which connects particularly to the bases of blankingtransistors 56 and 58 through current limiting resistors and 62,respectively. The output of AND gate 82 is supplied to a counter 80having stages, A. B. C. and D. The outputs from counter 80 are appliedin parallel as inputs to a decoder device 78. The particular counter anddecoder circuits form no part of the present invention, however, onesuch counter and decoder arrangement which provides a coded outputarrangement similar to that shown in FIGURE 2 can be seen in US. patentapplication Ser. No. 440,830, filed Mar. 18, 1965, and assigned toassignee of the present invention. The output from decoder 78 isillustrated by the time-waveform graphs shown in FIGURE 3. It can beseen that for every odd count in the counter, lead 64 becomes slightlynegative and lead 66 becomes positive, and for every even count in thecounter, lead 66 becomes slightly negative and lead 64 becomes positive.Decoder output lead 68, 70, 72, 74, and 76 become selectively positiverepresenting the counts of 0 or 1, 2 or 3, 4 or 5, 6 or 7 and 8 or 9,respectively. For example, if the counter 80 has received eight inputpulses, it can be seen by reference to FIGURE 3 that decoder output lead66 will be slightly negative and decoder output lead 76 will bepositive.

The driving transistors 52A through 52A and 54A through 54B are arrangedto provide driving signals to a ten-character Nixie tube display havingcharacters 0 through 9. The numerals appearing above the collectors ofthe respective driving transistors represent the character of the Nixietube responsive to the individual driving transistor. Odd characterdriving transistors 52A through 52E are connected to the collector ofblanking transistor 56, and even character driving transistors 54Athrough 54E have their emitters connected to the collector of blankingtransistor 58. The emitters of blanking transistors 56 and 58 areconnected respectively to the odd lead 64 and the even lead 66 fromdecoder 78.

The operation of FIGURE 2 is as follows: Assume the counter has receivedsix pulses from the source 88 through the AND gate 82 and that nofurther pulses are being received and accumulated bceause terminal 84 ishigh and the gate 82 is only conditioned by a low or negative voltagesignal at terminal 84. Having received the six input pulses, the stagesof counter 80 will be particular stable states depending upon the typeof counter used and the number of input pulses received. The outputwires of the counter which are connected to the input of the decoder 78are selectively energized in dependence upon the particular stablestates of the stages of counter 80. Under the conditions described, thedecoder output line 66 will be low or negative indicating an even countand decoder output line 74 will be positive indicating a count of either6 or 7. It can be seen. by referring to FIGURE 3 that the decoderprovides a negative output on the even line and a positive output on the6 or 7" line when the counter has accumulated six pulses. The signal onlead 74 is applied to the bases of transistors 52D and 54D. However, adriving negative potential is applied only to the emitter of transistor54D via line 66 and the emittercollector path of blanking transistor 58,and no driving voltage is applied to the emitter of transistor 52D.Thus, with conditioning signals applied to the base and emitter oftransistor 54D, that transistor becomes conductive causing the Nixietube to display the digit 6. The display continues to indicate the digit6 as long as neither a blanking signal is applied to blanking transistor58 nor the count in counter 80 changes.

If, for example, terminal 84 is connected to an analogto-time voltageconverter, and it is desirable to take readings periodically, a secondreading may be initiated in the counter by resetting the counter to 0 bymeans not shown, and providing the negative signal output of theanalog-to-time converter to energize AND gate 82 and blank the display.The width of the negative pulse at terminal 84 will be proportional tothe analog voltage being measured by the analog-to-time converter, and,consequently, the number of pulses passed through AND gate 82 from pulsesource 88 will be proportional to the analog voltage being measured.Also, the negative voltage at terminal 84 is connected via lead 86 andcurrent limiting resistors 60 and 62 to the bases of blankingtransistors 56 and 58. The blanking transistors 56 and 58 consequentlybecome non-conducting during the accumulation period and prevent drivingcurrents from being supplied to the emitters of the driving transistors52A through 52E and 54A. During the accumulation period the counter 80will accumulate the pulses supplied thereto by the pulse source 88 andthe output of the decoder 78 will be changing with each additional pulseinput to the counter. However, since the display is blanked by theblanking transistors 56 and 58, the outputs from the decoder 78 will notcause a blur on the Nixie tube display. The termination of the negativepulse at terminal 84 ends the accumulation period and at the same timeremoves the blanking signal from the bases of transistors 56 and 58. Theoutput of the decoder 78 which is now a coded indication of the numberof pulses accumulated by the counter energizes a particular drivingtransistor in the manner described above.

Although preferred embodiments of the invention have been describedabove, particularly FIGURE 2 which shows a specific arrangement of oneblanking transistor per five driving transistors, it should be apparentthat the number of driving transistors and blanking transistors may varyin dependence upon the code used and the number of Nixie display tubesused. The invention contemplates primarily the use of a blankingtransistor for isolating one of the conditioning signals from a drivingtransistor which can become conductive only upon the application of twoconditioning signals being applied thereto.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is:

1. A blanking circuit for a display tube of the type having a pluralityof cathodes each corresponding to a different character to be displayed,said display tube adapted to display a numerical indication of the countaccumulated by a counter which receives pulses only during the presenceof a gating pulse and whose output is applied to a decoder, said decoderhaving a first pair of outputs and a second plurality of outputsindicating the count in said counter, comprising (a) a first and secondgroup of driving transistors each having emitter, base and collectorterminals, each having its collector terminal connected to a difierentcathode of said display tube and energized by a conditioning signal ontheir respective base terminals and a driving signal on their respectiveemitter terminals,

(b) a first emitter drive line connected to the emitter terminals ofsaid first group of driving transistors,

(c) a second emitter drive line connected to the emitter terminals ofsaid second group of driving transistors,

(d) a first blanking transistor having emitter, base and collectorterminals connected to said first emitter drive line,

(e) a second blanking transistor having emitter, base and collectorterminals connected to said second emitter drive line,

( f) means for applying conditioning signals selectively to the baseterminals of said first and second group of driving transistors, saidlatter means comprising connections between said second plurality ofoutputs of said decoder and the base terminals of said drivingtransistors respectively,

(g) means for applying driving signals to said first and second emitterdrive lines through the emittercollector paths of said first and secondblanking transistors respectively, said latter means comprisingconnections between said first pair of outputs of said decoder,indicating respectively odd and even counts in said counter, and theemitter terminals of said first and second blanking transistors, and

(b) means for applying blanking signals to the base terminals of saidfirst and second blanking transistors for causing said first and secondblanking transistors to become non-conductive.

References Cited UNITED STATES PATENTS 2,766,444 10/ 1956 Sheftelman340318 2,933,644 4/1960 Hupp 315--84.5 3,008,067 11/1961 Somlyody340-168 X 3,020,418 2/1962 Emile 30788.5 3,304,548 2/1967 Klinikowski235-92 XR ARTHUR GAUSS, Primary Examiner.

J. ZAZWORSKY, Assistant Examiner.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,395,268 July 30, 1968 David M. Barton It is certified that errorappears in the above identified patent and that said Letters Patent arehereby corrected as shown below:

Column 1, line 28, "This" should read The Column 3, line 12, after "22"insert a period; line 57, "A.B.C." should read A,B,C, line 73, after "7"insert a comma. Column 4, line 3, "52A through 52A" should read 52Athrough 5213 line 22, "will beparticular" should read will be inparticular line 63, after "54A insert through 54E Signed and sealed this13th day of January 1970.

(SEAL) Attest:

Edward M. Fletcher, Jr. WILLIAM E. SCHUYLER, JR. Attesting OfficerCommissioner of Patents

